int bf0_pll_calibration()
{
uint32_t pll_cnt;
uint32_t xtal_cnt;
uint32_t fc_vco;
uint32_t fc_vco_min;
uint32_t fc_vco_max;
uint32_t delta_cnt;
uint32_t delta_cnt_min;
uint32_t delta_cnt_max;
uint32_t delta_fc_vco;
uint32_t target_cnt;
HAL_PMU_EnableAudio(1);
HAL_RCC_EnableModule(RCC_MOD_AUDCODEC);
HAL_TURN_ON_PLL();
// VCO frequency calibration
hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_OPEN;
hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_EN_LF_VCIN;
hwp_audcodec->PLL_CAL_CFG = (0 << AUDCODEC_PLL_CAL_CFG_EN_Pos) |
(2000 << AUDCODEC_PLL_CAL_CFG_LEN_Pos);
for (int i = 0; i < sizeof(g_pll_vco_tab) / sizeof(g_pll_vco_tab\[0\]); i++)
{
target_cnt = g_pll_vco_tab\[i\].target_cnt;
fc_vco = 16;
delta_fc_vco = 8;
// setup calibration and run
// target pll_cnt = ceil(46MHz/48MHz\*2000)+1 = 1918
// target difference between pll_cnt and xtal_cnt should be less than 1
while (delta_fc_vco != 0)
{
hwp_audcodec->PLL_CFG0 &= \~AUDCODEC_PLL_CFG0_FC_VCO;
hwp_audcodec->PLL_CFG0 |= (fc_vco << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
hwp_audcodec->PLL_CAL_CFG |= AUDCODEC_PLL_CAL_CFG_EN;
while (!(hwp_audcodec->PLL_CAL_CFG & AUDCODEC_PLL_CAL_CFG_DONE_Msk)) {
rt_kprintf("delta_fc_vco %x \\r\\n", hwp_audcodec->PLL_CAL_CFG);
};
pll_cnt = (hwp_audcodec->PLL_CAL_RESULT >> AUDCODEC_PLL_CAL_RESULT_PLL_CNT_Pos);
xtal_cnt = (hwp_audcodec->PLL_CAL_RESULT & AUDCODEC_PLL_CAL_RESULT_XTAL_CNT_Msk);
hwp_audcodec->PLL_CAL_CFG &= \~AUDCODEC_PLL_CAL_CFG_EN;
if (pll_cnt < target_cnt)
{
fc_vco = fc_vco + delta_fc_vco;
delta_cnt = target_cnt - pll_cnt;
}
else
{
fc_vco = fc_vco - delta_fc_vco;
delta_cnt = pll_cnt - target_cnt;
}
delta_fc_vco = delta_fc_vco >> 1;
rt_kprintf("delta_fc_vco %d \\r\\n", delta_fc_vco);
}
rt_kprintf("call par CFG1(%x)\\r\\n", hwp_audcodec->PLL_CFG1);
After power-up, it is stuck in the loop below. The print statement was added by me.
while (!(hwp_audcodec->PLL_CAL_CFG & AUDCODEC_PLL_CAL_CFG_DONE_Msk)) {
rt_kprintf("delta_fc_vco %x \\r\\n", hwp_audcodec->PLL_CAL_CFG);
};
The log is as follows:
09-21 00:10:53:526 SFBL
09-21 00:10:54:041 Serial:c2,Chip:4,Package:3,Rev:3 Reason:00000080
09-21 00:10:54:043 \ | /
09-21 00:10:54:045 - SiFli Corporation
09-21 00:10:54:046 / | \ build on Sep 6 2026, 2.5.0 build edb6cf67
09-21 00:10:54:048 2020 - 2022 Copyright by SiFli team
09-21 00:10:54:050 cal data cc_mn:12 cc_mp:15 cv_vctrl:36 prog_vlp2:7
09-21 00:10:54:052 mount /dev sucess
09-21 00:10:54:053 lwIP-2.0.3 initialized!
09-21 00:10:54:054 [BUS]spi1 probe sdcard…
09-21 00:10:54:058 I/sifli_charge ISR: eoc: 1
09-21 00:10:54:059 [SD] no card (pin 27), skip msd_init
09-21 00:10:54:061 I/drv.rtc main: PSCLR=0x80000100 DivAI=128 DivAF=0 B=256
09-21 00:10:54:064 I/drv.rtc main: RTC use LXT RTC_CR=00000001
09-21 00:10:54:066 I/drv.rtc main: Init RTC, wake = 0
09-21 00:10:54:067 I/drv.audprc main: init 00 ADC_PATH_CFG0 0x606
09-21 00:10:54:069 I/drv.audprc main: HAL_AUDPRC_Init res 0
09-21 00:10:54:070 I/drv.audcodec main: HAL_AUDCODEC_Init res 0
09-21 00:10:54:073 [32;22m[I/FAL] Flash Abstraction Layer (V0.5.99) initialize success.[0m
09-21 00:10:54:076 [32;22m[I/FAL] The FAL MTD NOR device (dfu) created successfully[0m
09-21 00:10:54:083 [32;22m[I/FAL] The FAL MTD NOR device (ble) created successfully[0m
09-21 00:10:54:088 delta_fc_vco 7d00001
09-21 00:10:54:090 delta_fc_vco 7d00001
09-21 00:10:54:092 delta_fc_vco 7d00001
09-21 00:10:54:093 delta_fc_vco 7d00001
09-21 00:10:54:095 delta_fc_vco 7d00001
What is the cause of this? This occurred during testing with a new board; the previous boards did not have this issue.