/*Auto generated configuration*/
#ifndef RT_CONFIG_H
#define RT_CONFIG_H

#define KCONFIG_V2 1
#define BSP_USING_RTTHREAD 1
#define RT_USING_COMPONENTS_INIT 1
#define RT_USING_USER_MAIN 1
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_FINSH 1
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY 1
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB 1
#define FINSH_USING_DESCRIPTION 1
#define FINSH_ECHO_DISABLE_DEFAULT 1
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH 1
#define FINSH_USING_MSH_DEFAULT 1
#define FINSH_ARG_MAX 10
#define RT_USING_DFS 1
#define DFS_USING_WORKDIR 1
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT 1
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS 1
#define RT_DFS_ELM_USE_LFN_3 1
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT 1
#define RT_USING_DFS_DEVFS 1
#define RT_USING_DEVICE_IPC 1
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL 1
#define RT_SERIAL_USING_DMA 1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_SERIAL_DEFAULT_BAUDRATE 1000000
#define RT_USING_HWTIMER 1
#define RT_USING_I2C 1
#define RT_USING_I2C_BITOPS 1
#define RT_USING_PIN 1
#define RT_USING_PWM 1
#define RT_USING_MTD_NAND 1
#define RT_USING_SDIO 1
#define RT_SDIO_STACK_SIZE 2048
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 2048
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_MMCSD_USER_OFFSET 0
#define RT_USING_AUDIO 1
#define RT_USING_USB_DEVICE 1
#define RT_USBD_THREAD_STACK_SZ 4096
#define USB_VENDOR_ID 0x0FFE
#define USB_PRODUCT_ID 0x0001
#define RT_USB_DEVICE_COMPOSITE 1
#define RT_USB_DEVICE_NONE 1
#define RT_USB_DEVICE_MSTORAGE 1
#define RT_USB_MSTORAGE_DISK_NAME "sd0"
#define RT_USING_LIBC 1
#define RT_USING_POSIX 1
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32 1
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK 1
#define IDLE_THREAD_STACK_SIZE 512
#define RT_USING_TIMER_SOFT 1
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 1024
#define RT_DEBUG 1
#define RT_USING_SEMAPHORE 1
#define RT_USING_MUTEX 1
#define RT_USING_EVENT 1
#define RT_USING_MAILBOX 1
#define RT_USING_MESSAGEQUEUE 1
#define RT_USING_MEMPOOL 1
#define RT_USING_SMALL_MEM 1
#define RT_USING_HEAP 1
#define RT_USING_DEVICE 1
#define RT_USING_CONSOLE 1
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x30103
#define BSP_USING_FULL_ASSERT 1
#define ROM_ATT_BUF_SIZE 3084
#define ROM_LOG_SIZE 4096
#define LCPU_RUN_ROM_COMBINE_RAM 1
#define BT_DUAL_HOST_MEM 1
#define MB_PORT 1
#define HCI_ON_LOG 1
#define LOG_ON_CONSOLE 1
#define HCI_LOG_SIZE 131072
#define IPC_USE_CONSOLE_DEVICE 1
#define USING_PARTITION_TABLE 1
#define OPT_LEVEL_SIZE 1
#define OPT_LEVEL "-Oz"
#define KCONFIG_BOARD_V2 1
#define SOC_SF32LB56X 1
#define BF0_HCPU 1
#define CORE "HCPU"
#define CPU "Cortex-M33"
#define LXT_FREQ 32768
#define LXT_LP_CYCLE 200
#define BT_TX_POWER_VAL 1
#define BT_TX_POWER_VAL_MAX 0
#define BT_TX_POWER_VAL_MIN 0
#define BT_TX_POWER_VAL_INIT 0
#define LCPU_CONFIG_AUTO 1
#define BSP_USING_DMA 1
#define BSP_USING_UART 1
#define BSP_USING_UART1 1
#define BSP_UART1_RX_USING_DMA 1
#define BSP_USING_I2C 1
#define BSP_USING_I2C1 1
#define BSP_USING_TIM 1
#define BSP_USING_LPTIM1 1
#define BSP_USING_PWM 1
#define BSP_USING_PWM4 1
#define BSP_USING_MPI 1
#define BSP_USING_SPI_FLASH 1
#define BSP_ENABLE_MPI1 1
#define BSP_ENABLE_QSPI1 1
#define BSP_MPI1_MODE_3 1
#define BSP_QSPI1_MODE 3
#define BSP_USING_PSRAM1 1
#define BSP_QSPI1_MEM_SIZE 8
#define BSP_ENABLE_MPI2 1
#define BSP_ENABLE_QSPI2 1
#define BSP_MPI2_MODE_5 1
#define BSP_QSPI2_MODE 5
#define BSP_USING_PSRAM2 1
#define BSP_QSPI2_MEM_SIZE 4
#define BSP_ENABLE_MPI3 1
#define BSP_ENABLE_QSPI3 1
#define BSP_MPI3_MODE_1 1
#define BSP_QSPI3_MODE 1
#define BSP_QSPI3_USING_DMA 1
#define BSP_USING_NAND_FLASH3 1
#define BSP_QSPI3_MEM_SIZE 128
#define BSP_USING_SPI_NAND 1
#define BSP_USING_EXT_DMA 1
#define BSP_USING_HW_AES 1
#define BSP_USING_PSRAM 1
#define BSP_USING_USBD 1
#define BSP_USING_EPIC 1
#define EZIP_PAL_SUPPORT 1
#define BSP_USING_LCDC 1
#define BSP_USING_SDIO 1
#define BSP_USING_SDHCI 1
#define SD_MMC_DDR_SUPPORT 1
#define SD_MMC_OLINE_SUPPORT 1
#define BSP_USING_SDHCI1 1
#define SD_MAX_FREQ 24000000
#define SD_DMA_MODE 2
#define SDIO_CARD_MODE 0
#define BSP_USING_PINMUX 1
#define BSP_USING_LCPU_PATCH 1
#define BSP_ENABLE_AUD_PRC 1
#define BSP_AUDPRC_TX0_DMA 1
#define BSP_AUDPRC_RX0_DMA 1
#define BSP_ENABLE_AUD_CODEC 1
#define BSP_USING_LCD 1
#define BSP_USING_BUILTIN_LCD 1
#define LCD_USING_HTM_H070A20_RGB_A01 1
#define LCD_HOR_RES_MAX 1024
#define LCD_VER_RES_MAX 600
#define LCD_DPI 315
#define BSP_USING_TOUCHD 1
#define TOUCH_DEVICE_NAME "i2c1"
#define TSC_USING_GT911 1
#define LCD_USING_HTM_H070A20 1
#define BSP_LCDC_USING_DPI 1
#define BSP_USING_RAMLESS_LCD 1
#define LCD_USING_PWM_AS_BACKLIGHT 1
#define BSP_USING_KEY1 1
#define BSP_KEY1_PIN 128
#define BSP_KEY1_ACTIVE_HIGH 1
#define PA_USING_AW8155 1
#define AW8155_GPIO_PIN 116
#define CONSOLE_UART1 1
#define BSP_USING_LED1 1
#define BSP_LED1_PIN 41
#define BSP_LED1_ACTIVE_HIGH 1
#define INSERT_DETE_USB_PIN 108
#define BSP_USING_BOARD_SF32LB56_LCD_A128R12N1 1
#define ASIC 1
#define TOUCH_IRQ_PIN 51
#define BSP_SUPPORT_DPI 1
#define LCD_PWM_BACKLIGHT_INTERFACE_NAME "pwm4"
#define LCD_PWM_BACKLIGHT_CHANEL_NUM 4
#define LCD_BACKLIGHT_CONTROL_PIN 119
#define LCD_EXTRA_SPI_CS_PIN 04
#define LCD_EXTRA_SPI_CLK_PIN 17
#define LCD_EXTRA_SPI_MOSI_PIN 18
#define CUSTOM_MEM_MAP 1
#endif
