Is it normal that a DAC chip cannot be used due to what appears to be a specific clock limitation in SF32LB52? In drv_i2s_audio.c, the clock divider is set to 8, and the expected I2S clock is noted as 6.144 MHz, but the printed actual frequency is only 1.024 MHz. Is this correct?

[sumsum]

[sumsum]

If the final effective frequency is 1.024 MHz, subsequent use of the txrx_clk_div parameter seems to cause issues.

[ljq-ctrl]

The src_clk_freq in the code is only assigned but not used anywhere.

For 55x, \__HAL_I2S_CLK_XTAL() is called, which uses 48M.
Others call \__HAL_I2S_CLK_PLL(), which uses 49.152M.

To change the frequency, refer to https://gitee.com/SiFli/sifli-sdk/blob/main/rtos/rtthread/bsp/sifli/drivers/drv_i2s_audio.c
and check I2S_USE_DOUBLE_MCLK, where I2S_USE_DOUBLE_MCLK is defined as 1.

[sumsum]

How can I limit the BCLK under a fixed audio format? Is it mainly by modifying the txrx_clk_div parameter?

[Kingjt656]

As mentioned above, just take the latest drv_i2s_audio.c code and set I2S_USE_DOUBLE_MCLK to 1. The fourth parameter in CLK_DIV_T is used to adjust the bclk.