Question about I2S performance of 56

Troubleshooting
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  1. The manual states: “Configurable I2S PCM signal bit width, up to 24-bit”. If a 32-bit DAC such as CS43131 is connected to I2S, will it be unable to fully utilize the performance of the external DAC?

  2. In “Table 3-2: Common Interface Rates”, the maximum rate of I2S is 48KHz. This speed is said to be the sampling rate. Is it the recording rate for receiving data from an I2S microphone? And the 32-bit mentioned there, is that also the recording rate?

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Please answer. Please answer. Please answer.

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  1. No, the PCM signal bit width of I2S is not necessarily all valid bits. Currently, 24-bit is the maximum effective bit width of a DAC, with each bit corresponding to 6 dB of SNR. The theoretical maximum SNR for 24-bit is 144 dB, which exceeds all DACs available on the market. Even if a DAC’s I2S supports 32-bit, its effective bits will not exceed 24-bit. Therefore, 24-bit will not be a bottleneck for DAC performance; the key is the effective data bit width in the I2S protocol.
  2. I2S has two additional clocks: the LRCK sampling clock, which corresponds to 48 kHz. 32-bit refers to the number of bits per sample point, corresponding to the number of BCLK cycles in one LRCK cycle. For stereo, one LRCK cycle will contain 64 BCLK cycles.