SF32LB56 spi2 支持DMA吗

贾进 · 2025 年9 月 5 日 03:05

打开SPI2 的DMA，编译出现问题，参考SF32LB52的配置，合入spi2的DMA通道
#define SPI2_DMA_RX_IRQHandler DMAC1_CH5_IRQHandler
#define SPI2_RX_DMA_IRQ_PRIO 0
#define SPI2_RX_DMA_INSTANCE DMA1_Channel5
#define SPI2_RX_DMA_IRQ DMAC1_CH5_IRQn
#define SPI2_DMA_TX_IRQHandler DMAC1_CH8_IRQHandler
#define SPI2_TX_DMA_IRQ_PRIO 0
#define SPI2_TX_DMA_INSTANCE DMA1_Channel8
#define SPI2_TX_DMA_IRQ DMAC1_CH8_IRQn

发现是可以用的。
但是开了RGB的屏幕后，会发现死了。
是否两者配置有冲突？

pengwei · 2025 年9 月 5 日 10:19

SPI2与屏幕没有直接关系。可以检查下是不是DMA的通道冲突，或者IO冲突。

贾进 · 2025 年9 月 5 日 11:10

SPI2 改为中断模式就好了，确定是DMA的问题；屏幕接口如果改为QSPI的也没有问题，只有RGB接口存在问题；没看出RGB接口用的DMA那个通道。

贾进 · 2025 年9 月 8 日 01:46

下面是死机log ，可以帮忙分析一下是哪里问题吗？
09-08 09:35:44:643 [293736] I/ble_app KE_EVT2: advertising device 12: addr type: random, addr: 3a-f0-23-bd-c-7d
09-08 09:35:44:645 [293781] I/ble_app KE_EVT2: adv type: legacy adv, adv info: adv
09-08 09:35:44:646 [293808] I/ble_app KE_EVT2: adv tx pwr: 127, rssi: -98
09-08 09:35:44:647 D/HEX adv_data: 0000-0010: 1E FF 06 00 01 09 20 02 AF D8 8D 34 AD DE 58 F7 … …4..X.
09-08 09:35:44:649 0010-0020: 60 6A 46 53 3E A4 B1 19 53 19 F3 3B 1E 1D 9C `jFS>…S..;…
09-08 09:35:44:650 [293911] I/ble_app KE_EVT2:
09-08 09:35:45:099 [309073] I/ble_app KE_EVT2: Scan stopped 69
09-08 09:35:45:100 [309100] D/BLE_GAP KE_EVT2: evt 167, ret 0
09-08 09:35:49:087 [439886] I/spi2 timer: start sample
09-08 09:35:49:330 [447808] I/NO_TAG timer: power key released
09-08 09:35:49:979 [469073] E/drv.lcd lcd_task: draw_core timeout
09-08 09:35:49:980 [469096] E/drv.lcd lcd_task: Error, Clear p_drv_ops 140dcc4c, sem_v=0
09-08 09:35:49:981 [469127] E/drv.lcd lcd_task: irq_en=0
09-08 09:35:49:981 [469144] E/drv.lcd lcd_task: LCDC1_irq_en=1, active=0, pending=0
09-08 09:35:49:982 [469171] E/drv.lcd lcd_task: hlcdc errcode=0, lock=0, state=2
09-08 09:35:49:984 [469196] E/drv.lcd lcd_task: LCDC STATUS=0,TE=0
09-08 09:35:49:985 [469216] E/drv.lcd lcd_task: HAL dbg cnt 4e, 4e, 4d
09-08 09:35:49:986 [469238] E/drv.lcd lcd_task: DRV dbg cnt 4e, 4d, 4d
09-08 09:35:49:987 [469287] E/drv.lcd lcd_task: LCDC CANVAS TL=0,BR=3ff,SETTING=1ff0100,IRQ=50000
09-08 09:35:49:988 [469321] E/drv.lcd lcd_task: LCDC LAYER0 CFG=15000ff0,TL=0,BR=3ff,SRC=2009003c,DEC=0
09-08 09:35:49:990 [469357] E/drv.lcd lcd_task: LCDC LAYER1 CFG=0,TL=0,BR=0,SRC=0
09-08 09:35:49:991 [469548] E/drv.lcd lcd_task: LCDC CANVAS TL=0,BR=3ff
09-08 09:35:49:993 [469570] E/drv.lcd lcd_task: PTC_MEM4=10251, DMA_TC8=20074888
09-08 09:35:49:994 [469597] E/drv.lcd lcd_task: BTIM1 CR=0, PSC=0,ARR=0, EGR=0
09-08 09:35:49:995 [469623] E/drv.lcd lcd_task: BTIM2 CR=c, PSC=4,ARR=21f0, EGR=0
09-08 09:35:49:997 [469650] E/drv.lcd lcd_task: ERR: ptc_code[0,24]=0000001c, 0007007d
09-08 09:35:49:998 AllDMA(40001008):
09-08 09:35:49:998 00002ab0 00000000 00000000 00000000 00000000
09-08 09:35:49:999 00002aa0 00000000 00000000 00000000 00000000
09-08 09:35:50:000 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:002 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:002 0000258f 00003932 40016010 2007e888 00000000
09-08 09:35:50:003 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:004 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:006 0000059b 00002e47 40016010 2007e888 00000000
09-08 09:35:50:007 regs(40020010):
09-08 09:35:50:007 00000068 4000105c 00000020 00000000
09-08 09:35:50:008 0000001c 4000802c 2009003c 00000000
09-08 09:35:50:009 00000079 40017014 20090c58 00000000
09-08 09:35:50:009 0007007a 40017010 00000800 00000000
09-08 09:35:50:010 0000007b 4001700c 00000200 00000000
09-08 09:35:50:012 0005007f 400080bc 00000001 00000000
09-08 09:35:50:012 0006007d 400080bc fffffffe 00000000
09-08 09:35:50:013 0007001c 40001064 00000080 00000000
09-08 09:35:50:014 [470041] E/drv.lcd lcd_task: code phase 4
09-08 09:35:50:014 code(2008fa24):
09-08 09:35:50:015 00000068 4000105c 00000020 00000000
09-08 09:35:50:016 0000001c 4000802c 2009003c 00000000
09-08 09:35:50:016 00000079 40017014 20090c58 00000000
09-08 09:35:50:017 0007007a 40017010 00000800 00000000
09-08 09:35:50:018 0000007b 4001700c 00000200 00000000
09-08 09:35:50:018 0005007f 400080bc 00000001 00000000
09-08 09:35:50:018 0006007d 400080bc fffffffe 00000000
09-08 09:35:50:019 0007001c 40001064 00000080 00000000
09-08 09:35:50:068 [472054] E/drv.lcd lcd_task: Error, Clear p_drv_ops 140dcc4c, sem_v=0
09-08 09:35:50:070 [472085] E/drv.lcd lcd_task: irq_en=0
09-08 09:35:50:071 [472101] E/drv.lcd lcd_task: LCDC1_irq_en=1, active=0, pending=0
09-08 09:35:50:072 [472128] E/drv.lcd lcd_task: hlcdc errcode=0, lock=0, state=2
09-08 09:35:50:074 [472155] E/drv.lcd lcd_task: LCDC STATUS=0,TE=0
09-08 09:35:50:074 [472174] E/drv.lcd lcd_task: HAL dbg cnt 4e, 4e, 4d
09-08 09:35:50:076 [472196] E/drv.lcd lcd_task: DRV dbg cnt 4e, 4d, 4d
09-08 09:35:50:077 [472217] E/drv.lcd lcd_task: LCDC CANVAS TL=0,BR=3ff,SETTING=1ff0100,IRQ=50000
09-08 09:35:50:077 [472250] E/drv.lcd lcd_task: LCDC LAYER0 CFG=15000ff0,TL=0,BR=3ff,SRC=2009003c,DEC=0
09-08 09:35:50:078 [472286] E/drv.lcd lcd_task: LCDC LAYER1 CFG=0,TL=0,BR=0,SRC=0
09-08 09:35:50:081 [472500] E/drv.lcd lcd_task: LCDC CANVAS TL=0,BR=3ff
09-08 09:35:50:082 [472522] E/drv.lcd lcd_task: PTC_MEM4=10251, DMA_TC8=2007e888
09-08 09:35:50:085 [472549] E/drv.lcd lcd_task: BTIM1 CR=0, PSC=0,ARR=0, EGR=0
09-08 09:35:50:086 [472575] E/drv.lcd lcd_task: BTIM2 CR=c, PSC=4,ARR=21f0, EGR=0
09-08 09:35:50:087 [472602] E/drv.lcd lcd_task: ERR: ptc_code[0,24]=0000001c, 0007007d
09-08 09:35:50:088 AllDMA(40001008):
09-08 09:35:50:088 00002ab0 00000000 00000000 00000000 00000000
09-08 09:35:50:089 00002aa0 00000000 00000000 00000000 00000000
09-08 09:35:50:090 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:092 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:093 0000258b 00001021 40016010 2007e888 00000000
09-08 09:35:50:093 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:094 00000000 00000000 00000000 00000000 00000000
09-08 09:35:50:095 0000059b 00000583 40016010 2007e888 00000000
09-08 09:35:50:095 regs(40020010):
09-08 09:35:50:097 00000068 4000105c 00000020 00000000
09-08 09:35:50:098 0000001c 4000802c 2009003c 00000000
09-08 09:35:50:099 00000079 40017014 20090c58 00000000
09-08 09:35:50:100 0007007a 40017010 00000800 00000000
09-08 09:35:50:101 0000007b 4001700c 00000200 00000000
09-08 09:35:50:101 0005007f 400080bc 00000001 00000000
09-08 09:35:50:102 0006007d 400080bc fffffffe 00000000
09-08 09:35:50:105 0007001c 40001064 00000080 00000000
09-08 09:35:50:107 [472973] E/drv.lcd lcd_task: code phase 4
09-08 09:35:50:108 code(2008fa24):
09-08 09:35:50:109 00000068 4000105c 00000020 00000000
09-08 09:35:50:110 0000001c 4000802c 2009003c 00000000
09-08 09:35:50:110 00000079 40017014 20090c58 00000000
09-08 09:35:50:111 0007007a 40017010 00000800 00000000
09-08 09:35:50:111 0000007b 4001700c 00000200 00000000
09-08 09:35:50:112 0005007f 400080bc 00000001 00000000
09-08 09:35:50:112 0006007d 400080bc fffffffe 00000000
09-08 09:35:50:113 0007001c 40001064 00000080 00000000
09-08 09:35:50:114 [473134] I/drv.lcd lcd_task: [ON] → [TIMEOUT]
09-08 09:35:50:114 [473153] E/drv.lcd lcd_task: lcd_timeout_error draw_core, 1822
09-08 09:35:50:115 Assertion failed at function:draw_core, line number:1823 ,(0)
09-08 09:35:50:115 Previous ISR enable 0
09-08 09:35:50:116 ===================
09-08 09:35:50:117 Thread Info
09-08 09:35:50:117 ===================
09-08 09:35:50:118 pri status sp top stack size max used left tick error
09-08 09:35:50:118 -------- — ------- ---------- ---------- ---------- ------ ---------- —
09-08 09:35:50:119 KE_EVT3 10 suspend 0x2009bdc8 0x2009be3c 0x00000400 28% 0x0000000b 000
09-08 09:35:50:119 KE_EVT0 25 suspend 0x2009b8b8 0x2009b92c 0x00000400 11% 0x00000014 000
09-08 09:35:50:120 KE_EVT2 12 suspend 0x2009b340 0x2009b440 0x00001000 25% 0x00000011 000
09-08 09:35:50:121 tf_updat 3 suspend 0x20096a60 0x20096cb8 0x00000800 33% 0x00000003 000
09-08 09:35:50:156 adc_upda 3 suspend 0x200962b0 0x20096404 0x00000800 37% 0x00000006 000
09-08 09:35:50:157 by_conn 3 suspend 0x200947f8 0x200949f4 0x00000800 48% 0x00000012 000
09-08 09:35:50:158 lvgl_upd 3 suspend 0x200940c8 0x20094140 0x00000800 06% 0x00000014 000
09-08 09:35:50:158 lcd_task 12 ready 0x2006e1c8 0x2006e3fc 0x00000800 53% 0x00000002 000
09-08 09:35:50:162 tshell 20 suspend 0x2008f580 0x2008f700 0x00001000 16% 0x0000000a 000
09-08 09:35:50:163 usbd 8 suspend 0x2006f708 0x2006f7fc 0x00001000 06% 0x00000014 000
09-08 09:35:50:164 mmcsd_de 22 suspend 0x2006fef0 0x2006fffc 0x00000800 47% 0x00000003 000
09-08 09:35:50:164 tidle 31 ready 0x20009b40 0x20009b94 0x00000200 21% 0x00000013 000
09-08 09:35:50:165 timer 4 suspend 0x2006e720 0x2006e7fc 0x00000400 74% 0x00000009 000
09-08 09:35:50:165 main 19 suspend 0x2008ce60 0x2008d12c 0x00001000 54% 0x00000011 000
09-08 09:35:50:166 ===================
09-08 09:35:50:166 Mailbox Info
09-08 09:35:50:167 ===================
09-08 09:35:50:168 entry size suspend thread
09-08 09:35:50:169 -------- ---- ---- --------------
09-08 09:35:50:169 ble_app 0000 0008 0
09-08 09:35:50:170 mmcsdhot 0001 0004 0
09-08 09:35:50:173 mmcsdmb 0000 0004 1:mmcsd_de
09-08 09:35:50:173 ===================
09-08 09:35:50:174 MessageQueue Info
09-08 09:35:50:175 ===================
09-08 09:35:50:175 entry suspend thread
09-08 09:35:50:176 -------- ---- --------------
09-08 09:35:50:177 drv_lcd 0000 0
09-08 09:35:50:177 usbd 0000 1:usbd
09-08 09:35:50:178 ===================
09-08 09:35:50:178 Mutex Info
09-08 09:35:50:179 ===================
09-08 09:35:50:180 owner hold suspend thread
09-08 09:35:50:180 -------- -------- ---- --------------
09-08 09:35:50:181 fat0 tf_updat 0001 0
09-08 09:35:50:181 sdhci (null) 0000 0
09-08 09:35:50:182 sd_bus_l tf_updat 0001 0
09-08 09:35:50:183 ulog loc (null) 0000 0
09-08 09:35:50:184 fslock (null) 0000 0
09-08 09:35:50:184 i2c_bus_ (null) 0000 0
09-08 09:35:50:184 spi3 (null) 0000 0
09-08 09:35:50:186 spi2 adc_upda 0001 0
09-08 09:35:50:187 spi1 (null) 0000 0
09-08 09:35:50:187 ===================
09-08 09:35:50:188 Semaphore Info
09-08 09:35:50:189 ===================
09-08 09:35:50:189 v suspend thread
09-08 09:35:50:192 -------- — --------------
09-08 09:35:50:193 KE 000 1:KE_EVT3
09-08 09:35:50:194 KE 000 1:KE_EVT0
09-08 09:35:50:194 KE 000 1:KE_EVT2
09-08 09:35:50:195 full1 000 0
09-08 09:35:50:195 full0 000 0
09-08 09:35:50:195 empty1 000 0
09-08 09:35:50:197 empty0 000 0
09-08 09:35:50:198 sifli 000 0
09-08 09:35:50:198 lv_data 001 0
09-08 09:35:50:199 lv_lcd 000 0
09-08 09:35:50:199 lcd_msg 000 0
09-08 09:35:50:200 lcd_draw 000 0
09-08 09:35:50:201 drv_lcd 000 0
09-08 09:35:50:201 btn 001 0
09-08 09:35:50:202 shrx 000 0
09-08 09:35:50:202 epic 001 0
09-08 09:35:50:203 sem_sd0 000 0
09-08 09:35:50:203 sd_ack 000 0
09-08 09:35:50:204 aes_drv 001 0
09-08 09:35:50:205 drv_eDma 001 0
09-08 09:35:50:206 i2c1 000 0
09-08 09:35:50:206 spi3 000 0
09-08 09:35:50:208 spi2 000 1:adc_upda
09-08 09:35:50:209 spi1 000 0
09-08 09:35:50:209 heap 001 0
09-08 09:35:50:210 flash3 001 0
09-08 09:35:50:210 ===================
09-08 09:35:50:211 Memory Info
09-08 09:35:50:211 ===================
09-08 09:35:50:212 total memory: 162248 used memory : 65212 maximum allocated memory: 69332
09-08 09:35:50:212 ===================
09-08 09:35:50:213 MemoryHeap Info
09-08 09:35:50:213 ===================
09-08 09:35:50:214 pool size max used size available size
09-08 09:35:50:214 ------- ---------- ------------- --------------
09-08 09:35:50:215 =====================
09-08 09:35:50:216 PSP: 0x0x2006e2d4, MSP: 0x0x20001fe0
09-08 09:35:50:216 =====================
09-08 09:35:50:217 sp: 0x2006e330
09-08 09:35:50:217 psr: 0x40000000
09-08 09:35:50:218 r00: 0x00000000
09-08 09:35:50:218 r01: 0x00001c1f
09-08 09:35:50:219 r02: 0x00001753
09-08 09:35:50:220 r03: 0x30000000
09-08 09:35:50:220 r12: 0x14069919
09-08 09:35:50:221 lr: 0x140556db
09-08 09:35:50:222 pc: 0x20005fbc
09-08 09:35:50:223 =====================
09-08 09:35:50:223 fatal error on thread: lcd_task

yxhuang · 2025 年9 月 8 日 02:46

看起来你是在用DPI_AUX模式的屏幕，在56x上面会固定占用DMA1-Channel5：

需要确认下你现在用的是什么版本的代码？新版本上增加了动态DMA分配DMA_SUPPORT_DYN_CHANNEL_ALLOC，这部分代码需要更新才能使用。

贾进 · 2025 年9 月 8 日 05:57

非常感谢，确实这个问题，我目前:
SPI2 DMA 配置的是通道6，更改为下面通道后，问题解决。
#define SPI2_DMA_RX_IRQHandler DMAC1_CH6_IRQHandler
#define SPI2_RX_DMA_IRQ_PRIO 0
#define SPI2_RX_DMA_INSTANCE DMA1_Channel6
#define SPI2_RX_DMA_IRQ DMAC1_CH6_IRQn

system · 2025 年9 月 12 日 08:48

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