SF32LB56 SPI2 using DMA occasionally experiences a low-probability DMA timeout during boot, but works again after a restart.

  1. SPI2 DMA configuration is as follows:
#define SPI2_DMA_RX_IRQHandler    DMAC1_CH5_IRQHandler
#define SPI2_RX_DMA_IRQ_PRIO      0
#define SPI2_RX_DMA_INSTANCE      DMA1_Channel5
#define SPI2_RX_DMA_IRQ           DMAC1_CH5_IRQn
#define SPI2_DMA_TX_IRQHandler    DMAC1_CH8_IRQHandler
#define SPI2_TX_DMA_IRQ_PRIO      0
#define SPI2_TX_DMA_INSTANCE      DMA1_Channel8
#define SPI2_TX_DMA_IRQ           DMAC1_CH8_IRQn
  1. Software initialization configuration:
rt_device_t spi_bus = rt_device_find(SPI_BUS_NAME);

if (spi_bus)
{
    rt_device_open(spi_bus, RT_DEVICE_FLAG_RDWR);
    LOG_D("Find spi bus %s:%x\n", SPI_BUS_NAME, spi_bus);

    spi_dev_handle = (struct rt_spi_device *)rt_device_find(ADC_DEVICE_NAME);

    if (spi_dev_handle == NULL)
    {
        rst = rt_hw_spi_device_attach(SPI_BUS_NAME, ADC_DEVICE_NAME);
        spi_dev_handle = (struct rt_spi_device *)rt_device_find(ADC_DEVICE_NAME);

        if (spi_dev_handle == NULL)
        {
            LOG_E("Register spi_dev spi device fail\n");
            return -RT_ERROR;
        }
    }

    rst = rt_device_open((rt_device_t)(spi_dev_handle), 
                         RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX);

    spi_dev_cfg.data_width = 16;           // bits
    spi_dev_cfg.max_hz = ADC_SAMPLE_SPEED; // Hz
    spi_dev_cfg.mode = RT_SPI_MODE_3 | RT_SPI_MSB | RT_SPI_MASTER;
    spi_dev_cfg.frameMode = RT_SPI_TI;     // RT_SPI_MOTO; // RT_SPI_TI;

    rst = rt_spi_configure(spi_dev_handle, &spi_dev_cfg);
    LOG_D("rt_spi_configure result:%d", rst);
}
  1. Data reading:
rt_spi_transfer((struct rt_spi_device *)spi_dev_handle, ping_buffer, ping_buffer, ADC_BUFFER_SIZE);

It has been observed that, probabilistically, after certain power-on cycles, no data can be read — the system continuously experiences DMA timeout. However, the board functions normally again after a reboot.

If it occurs with low probability and fails stably, suspect there might be an issue with the module’s configuration. It is recommended to compare the register configurations of DMA and SPI when operating normally versus when errors occur.

Thank you for the reply. Is there a demo interface for printing DMA register via serial port?

Normal register status:

10-17 13:34:28:320 dma1 CCR1:0x2ab0, CCR2:0x2aa0
10-17 13:34:28:322 dma1 CCR3:0x0, CCR4:0x0
10-17 13:34:28:322 dma1 CCR5:0x258f, CCR6:0x0
10-17 13:34:28:323 dma1 CCR7:0x258f, CCR8:0x59b
10-17 13:34:28:323 dma1 CNDTR5:0x0, CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-17 13:34:28:324 dma1 CNDTR6:0x0, CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-17 13:34:28:325 dma1 CNDTR7:0x4b1b, CPAR7:0x40016010 CM0AR7:0x2002710c CBSR7:0x0
10-17 13:34:28:325 dma1 CNDTR8:0x4993, CPAR8:0x40016010 CM0AR8:0x2002710c CBSR8:0x0
10-17 13:34:28:326 spi2 TOP_CTRL:0xde3, FIFO_CTRL:0x20c00 INTE=0x4f TO=0x0
10-17 13:34:28:326 spi2 DATA:0x2080, STATUS:0x78141 PSP_CTRL=0x0 NW_CTRL=0x0
10-17 13:34:28:328 spi2 NW_STATUS:0x0, RWOT_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-17 13:34:28:330 spi2 CLK_CTRL:0x106, TRIWIRE_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0

Abnormal register status:

10-17 13:47:58:970 dma1 CCR1:0x2ab0, CCR2:0x2aa0
10-17 13:47:58:974 dma1 CCR3:0x0, CCR4:0x0
10-17 13:47:58:974 dma1 CCR5:0x258f, CCR6:0x0
10-17 13:47:58:975 dma1 CCR7:0x258f, CCR8:0x59b
10-17 13:47:58:975 dma1 CNDTR5:0x0, CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-17 13:47:58:976 dma1 CNDTR6:0x0, CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-17 13:47:58:976 dma1 CNDTR7:0x5000, CPAR7:0x40016010 CM0AR7:0x2002710c CBSR7:0x0
10-17 13:47:58:976 dma1 CNDTR8:0x4ffe, CPAR8:0x40016010 CM0AR8:0x2002710c CBSR8:0x0
10-17 13:47:58:977 spi2 TOP_CTRL:0xde3, FIFO_CTRL:0x20c00 INTE=0x4f TO=0x0
10-17 13:47:58:979 spi2 DATA:0x32e94f3f, STATUS:0x78142 PSP_CTRL=0x0 NW_CTRL=0x0
10-17 13:47:58:980 spi2 NW_STATUS:0x0, RWOT_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-17 13:47:58:981 spi2 CLK_CTRL:0x106, TRIWIRE_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0

Detected anomaly:

The STATUS register of spi2 shows 0x78142 during the abnormal case, while it is normally 0x78141. According to the specification:

[1] r 1’h0 CSS ClockSynchronizationStatus
  0: SPI controller is ready for slave clock operations
  1: SPI controller is currently busy synchronizing slave mode signals
[0] r 1’h0 BSY SPI controller Busy
  0: SPI controller is idle or disabled
  1: SPI controller is currently transmitting or receiving frame data

This indicates the SPI is in slave synchronization mode. It’s unclear how it entered this mode.

Additionally, the data register also shows an anomaly. Normally, it should contain 16-bit data, but here DATA:0x32e94f3f is clearly abnormal.

It appears that bits [2:1] FRF in the TOP_CTRL register are set to 1, indicating the TI SSP format. Please confirm if this is the intended configuration.

Yes, this happens in this mode, and I’ve also experienced it in MOTO mode.

Please confirm the behavior of this bit: After each timeout occurs, is this bit always 1? Does it remain 1 if read multiple times after the timeout? Also, after the issue occurs, please dump the registers of hpsys_rcc.

Every time this occurs, this bit is set to 1; I’ll dump it next Monday.

Normal condition registers:

10-20 09:20:17:531 dma1 CCR1:0x2ab0,CCR2:0x2aa0
10-20 09:20:17:531 dma1 CCR3:0x0,CCR4:0x0
10-20 09:20:17:532 dma1 CCR5:0x258f,CCR6:0x0
10-20 09:20:17:534 dma1 CCR7:0x258f,CCR8:0x59b
10-20 09:20:17:535 dma1 CNDTR5:0x0,CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-20 09:20:17:535 dma1 CNDTR6:0x0,CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-20 09:20:17:536 dma1 CNDTR7:0x4b18,CPAR7:0x40016010 CM0AR7:0x20027114 CBSR7:0x0
10-20 09:20:17:536 dma1 CNDTR8:0x4993,CPAR8:0x40016010 CM0AR8:0x20027114 CBSR8:0x0
10-20 09:20:17:537 spi2 TOP_CTRL:0xde3,FIFO_CTRL:0x20c00 INTE =0x4f TO = 0x0
10-20 09:20:17:537 spi2 DATA:0xffff,STATUS:0x78141 PSP_CTRL =0x0 NW_CTRL = 0x0
10-20 09:20:17:538 spi2 NW_STATUS:0x0,RWOT_CTRL:0x0 RWOT_CCM =0x0 RWOT_CVWRN = 0x0
10-20 09:20:17:541 spi2 CLK_CTRL:0x106,TRIWIRE_CTRL:0x0 RWOT_CCM =0x0 RWOT_CVWRN = 0x0
10-20 09:20:17:541 hwp_hpsys_rcc RSTR1:0x0,RSTR2:0x0 ENR1 =0x18f0fc8f ENR2 = 0x18005f
10-20 09:20:17:541 hwp_hpsys_rcc CSR:0x213a3,CFGR:0x5101 USBCR =0x4 DLL1CR = 0x8001da65
10-20 09:20:17:542 hwp_hpsys_rcc DLL2CR:0x8001da6d,DLL3CR:0x8001da6d HRCCAL1 =0x3fff HRCCAL2 = 0x0
10-20 09:20:17:542 hwp_hpsys_rcc DBGCLKR:0x4040400,DBGR:0x0 DWCFGR =0x19030

Abnormal condition registers:

10-20 09:21:45:251 dma1 CCR1:0x2ab0,CCR2:0x2aa0
10-20 09:21:45:252 dma1 CCR3:0x0,CCR4:0x0
10-20 09:21:45:253 dma1 CCR5:0x258f,CCR6:0x0
10-20 09:21:45:254 dma1 CCR7:0x258f,CCR8:0x59b
10-20 09:21:45:254 dma1 CNDTR5:0x0,CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-20 09:21:45:255 dma1 CNDTR6:0x0,CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-20 09:21:45:255 dma1 CNDTR7:0x5000,CPAR7:0x40016010 CM0AR7:0x20031114 CBSR7:0x0
10-20 09:21:45:255 dma1 CNDTR8:0x4ffe,CPAR8:0x40016010 CM0AR8:0x20031114 CBSR8:0x0
10-20 09:21:45:256 spi2 TOP_CTRL:0xde3,FIFO_CTRL:0x20c00 INTE =0x4f TO = 0x0
10-20 09:21:45:257 spi2 DATA:0x386391bf,STATUS:0x78142 PSP_CTRL =0x0 NW_CTRL = 0x0
10-20 09:21:45:257 spi2 NW_STATUS:0x0,RWOT_CTRL:0x0 RWOT_CCM =0x0 RWOT_CVWRN = 0x0
10-20 09:21:45:258 spi2 CLK_CTRL:0x106,TRIWIRE_CTRL:0x0 RWOT_CCM =0x0 RWOT_CVWRN = 0x0
10-20 09:21:45:258 hwp_hpsys_rcc RSTR1:0x0,RSTR2:0x0 ENR1 =0x18f0fc8f ENR2 = 0x18005f
10-20 09:21:45:258 hwp_hpsys_rcc CSR:0x213a3,CFGR:0x5101 USBCR =0x4 DLL1CR = 0x8001da65
10-20 09:21:45:260 hwp_hpsys_rcc DLL2CR:0x8001da6d,DLL3CR:0x8001da6d HRCCAL1 =0x3fff HRCCAL2 = 0x0
10-20 09:21:45:260 hwp_hpsys_rcc DBGCLKR:0x4040400,DBGR:0x0 DWCFGR =0x19030

No differences were found in hwp_hpsys_rcc configuration.

Does this bit become 1 every time after a timeout occurs? And does it remain 1 when read multiple times after the timeout?

Yes, this bit is always 1 after each timeout, and remains 1 upon multiple reads. The system cannot function properly unless rebooted and restarted.

Normal condition registers:

10-20 09:20:17:531 dma1 CCR1:0x2ab0, CCR2:0x2aa0
10-20 09:20:17:531 dma1 CCR3:0x0, CCR4:0x0
10-20 09:20:17:532 dma1 CCR5:0x258f, CCR6:0x0
10-20 09:20:17:534 dma1 CCR7:0x258f, CCR8:0x59b
10-20 09:20:17:535 dma1 CNDTR5:0x0, CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-20 09:20:17:535 dma1 CNDTR6:0x0, CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-20 09:20:17:536 dma1 CNDTR7:0x4b18, CPAR7:0x40016010 CM0AR7:0x20027114 CBSR7:0x0
10-20 09:20:17:536 dma1 CNDTR8:0x4993, CPAR8:0x40016010 CM0AR8:0x20027114 CBSR8:0x0
10-20 09:20:17:537 spi2 TOP_CTRL:0xde3, FIFO_CTRL:0x20c00 INTE=0x4f TO=0x0
10-20 09:20:17:537 spi2 DATA:0xffff, STATUS:0x78141 PSP_CTRL=0x0 NW_CTRL=0x0
10-20 09:20:17:538 spi2 NW_STATUS:0x0, RWOT_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-20 09:20:17:541 spi2 CLK_CTRL:0x106, TRIWIRE_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-20 09:20:17:541 hwp_hpsys_rcc RSTR1:0x0, RSTR2:0x0 ENR1=0x18f0fc8f ENR2=0x18005f
10-20 09:20:17:541 hwp_hpsys_rcc CSR:0x213a3, CFGR:0x5101 USBCR=0x4 DLL1CR=0x8001da65
10-20 09:20:17:542 hwp_hpsys_rcc DLL2CR:0x8001da6d, DLL3CR:0x8001da6d HRCCAL1=0x3fff HRCCAL2=0x0
10-20 09:20:17:542 hwp_hpsys_rcc DBGCLKR:0x4040400, DBGR:0x0 DWCFGR=0x19030

Abnormal condition registers:

10-20 09:21:45:251 dma1 CCR1:0x2ab0, CCR2:0x2aa0
10-20 09:21:45:252 dma1 CCR3:0x0, CCR4:0x0
10-20 09:21:45:253 dma1 CCR5:0x258f, CCR6:0x0
10-20 09:21:45:254 dma1 CCR7:0x258f, CCR8:0x59b
10-20 09:21:45:254 dma1 CNDTR5:0x0, CPAR5:0x0 CM0AR5:0x0 CBSR5:0x0
10-20 09:21:45:255 dma1 CNDTR6:0x0, CPAR6:0x0 CM0AR6:0x0 CBSR6:0x0
10-20 09:21:45:255 dma1 CNDTR7:0x5000, CPAR7:0x40016010 CM0AR7:0x20031114 CBSR7:0x0
10-20 09:21:45:255 dma1 CNDTR8:0x4ffe, CPAR8:0x40016010 CM0AR8:0x20031114 CBSR8:0x0
10-20 09:21:45:256 spi2 TOP_CTRL:0xde3, FIFO_CTRL:0x20c00 INTE=0x4f TO=0x0
10-20 09:21:45:257 spi2 DATA:0x386391bf, STATUS:0x78142 PSP_CTRL=0x0 NW_CTRL=0x0
10-20 09:21:45:257 spi2 NW_STATUS:0x0, RWOT_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-20 09:21:45:258 spi2 CLK_CTRL:0x106, TRIWIRE_CTRL:0x0 RWOT_CCM=0x0 RWOT_CVWRN=0x0
10-20 09:21:45:258 hwp_hpsys_rcc RSTR1:0x0, RSTR2:0x0 ENR1=0x18f0fc8f ENR2=0x18005f
10-20 09:21:45:258 hwp_hpsys_rcc CSR:0x213a3, CFGR:0x5101 USBCR=0x4 DLL1CR=0x8001da65
10-20 09:21:45:260 hwp_hpsys_rcc DLL2CR:0x8001da6d, DLL3CR:0x8001da6d HRCCAL1=0x3fff HRCCAL2=0x0
10-20 09:21:45:260 hwp_hpsys_rcc DBGCLKR:0x4040400, DBGR:0x0 DWCFGR=0x19030

No configuration differences were found in hwp_hpsys_rcc.

Is this bit always set to 1 after each timeout? And does it remain 1 when read multiple times after the timeout?

Yes, this bit is always 1 after each timeout, and remains 1 upon repeated reads. The system cannot function properly unless it is rebooted and restarted.

Additionally found:

Abnormal boot log:

10-20 09:29:42:363 \\ | /\
10-20 09:29:42:365 - SiFli Corporation
10-20 09:29:42:368 / | \\ build on Oct 16 2025, 2.4.0 build acc30fb1
10-20 09:29:42:368 2020 - 2022 Copyright by SiFli team
10-20 09:29:42:368 mount /dev success
10-20 09:29:42:370 [1330] I/drv.sdhci main: rt_hw_sdmmc_init 1 begin
10-20 09:29:42:386 [2012] I/drv.sdhci main: host version = 2
10-20 09:29:42:387 [2031] I/drv.sdhci main: SDHCI clock 288000000
10-20 09:29:42:388 [2051] I/drv.sdhci main: Maximum Clock Supported by HOST : 288 MHz
10-20 09:29:42:389 [2079] I/drv.sdhci main: host minclock 400000 host maxclock 288000000
10-20 09:29:42:390 [2110] I/drv.sdhci main: SDHCI controller on sdmmc using DMA
10-20 09:29:42:391 [2136] I/drv.sdhci main: Add host success
10-20 09:29:42:392 [2154] I/drv.sdhci main: rt_hw_sdmmc_init 1 done
10-20 09:29:42:393 [2179] I/drv.audprc main: init 00 ADC_PATH_CFG0 0x924
10-20 09:29:42:393 [2202] I/drv.audprc main: HAL_AUDPRC_Init res 0
10-20 09:29:42:394 [2224] I/drv.audcodec main: HAL_AUDCODEC_Init res 0
10-20 09:29:42:395 call par CFG1(35bb)
10-20 09:29:42:396 fc 9, xtal 2000, pll 2096
10-20 09:29:42:397 call par CFG1(35bb)
10-20 09:29:42:397 fc 7, xtal 2000, pll 1678
10-20 09:29:42:398 clock 0Hz busmode 1 powermode 1 cs 0 Vdd 23 width 0
10-20 09:29:42:408 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:29:42:408 [2745] I/drv.sdhci mmcsd_de: sdhci_set_clock2 400000
10-20 09:29:42:420 [3082] I/SDIO mmcsd_de: detect SDIO begin
10-20 09:29:42:420 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:29:42:421 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:29:42:423 [3233] I/SDIO mmcsd_de: detect SD card BEGIN
10-20 09:29:42:424 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:29:42:425 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:29:42:428 [3394] I/SDIO mmcsd_de: detect MMC begin
10-20 09:29:42:428 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:29:42:431 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:29:45:397 mount fs on flash to root fail
10-20 09:29:45:398 spi1 demo end!
10-20 09:29:45:400 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:29:45:402 SPI_EndRxTxTransaction 2003b3fc
10-20 09:29:45:403 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:29:45:403 SPI_EndRxTxTransaction 2003b3fc
10-20 09:29:45:403 [100767] E/DFS tfcard_s: can’t find mounted filesystem on this path:/mmwave
10-20 09:29:45:404 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:29:45:405 SPI_EndRxTxTransaction 2003b3fc
10-20 09:29:45:406 [100834] E/spi2 tfcard_s: mkdir ADC failed
10-20 09:29:45:407 LittlevGL and UI initialized successfully.
10-20 09:29:45:407 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:29:45:407 SPI_EndRxTxTransaction 2003b3fc

Normal boot log:

10-20 09:33:19:401 \\ | /\
10-20 09:33:19:403 - SiFli Corporation
10-20 09:33:19:404 / | \\ build on Oct 16 2025, 2.4.0 build acc30fb1
10-20 09:33:19:405 2020 - 2022 Copyright by SiFli team
10-20 09:33:19:405 mount /dev success
10-20 09:33:19:406 [1332] I/drv.sdhci main: rt_hw_sdmmc_init 1 begin
10-20 09:33:19:425 [2014] I/drv.sdhci main: host version = 2
10-20 09:33:19:426 [2033] I/drv.sdhci main: SDHCI clock 288000000
10-20 09:33:19:426 [2053] I/drv.sdhci main: Maximum Clock Supported by HOST : 288 MHz
10-20 09:33:19:428 [2082] I/drv.sdhci main: host minclock 400000 host maxclock 288000000
10-20 09:33:19:429 [2112] I/drv.sdhci main: SDHCI controller on sdmmc using DMA
10-20 09:33:19:430 [2139] I/drv.sdhci main: Add host success
10-20 09:33:19:430 [2157] I/drv.sdhci main: rt_hw_sdmmc_init 1 done
10-20 09:33:19:431 [2181] I/drv.audprc main: init 00 ADC_PATH_CFG0 0x924
10-20 09:33:19:433 [2204] I/drv.audprc main: HAL_AUDPRC_Init res 0
10-20 09:33:19:434 [2226] I/drv.audcodec main: HAL_AUDCODEC_Init res 0
10-20 09:33:19:435 call par CFG1(35bb)
10-20 09:33:19:436 fc 9, xtal 2000, pll 2096
10-20 09:33:19:436 call par CFG1(35bb)
10-20 09:33:19:437 fc 7, xtal 2000, pll 1676
10-20 09:33:19:437 clock 0Hz busmode 1 powermode 1 cs 0 Vdd 23 width 0
10-20 09:33:19:447 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:33:19:447 [2747] I/drv.sdhci mmcsd_de: sdhci_set_clock2 400000
10-20 09:33:19:457 [3084] I/SDIO mmcsd_de: detect SDIO begin
10-20 09:33:19:458 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:33:19:461 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:33:19:463 [3236] I/SDIO mmcsd_de: detect SD card BEGIN
10-20 09:33:19:464 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:33:19:464 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:33:19:467 [3396] I/SDIO mmcsd_de: detect MMC begin
10-20 09:33:19:468 clock 400000Hz busmode 1 powermode 2 cs 1 Vdd 23 width 0
10-20 09:33:19:469 clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 23 width 0
10-20 09:33:22:436 mount fs on flash to root fail
10-20 09:33:22:437 spi1 demo end!
10-20 09:33:22:439 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:33:22:441 SPI_EndRxTxTransaction 2003b3fc
10-20 09:33:22:441 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:33:22:441 SPI_EndRxTxTransaction 2003b3fc
10-20 09:33:22:442 [100769] E/DFS tfcard_s: can’t find mounted filesystem on this path:/mmwave
10-20 09:33:22:443 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:33:22:443 SPI_EndRxTxTransaction 2003b3fc
10-20 09:33:22:444 [100835] E/spi2 tfcard_s: mkdir ADC failed
10-20 09:33:22:445 LittlevGL and UI initialized successfully.
10-20 09:33:22:446 HAL_SPI_Transmit 2003b3fc,data=200405ec,size=3
10-20 09:33:22:446 SPI_EndRxTxTransaction 2003b3fc

Found:

There is a difference in the parameter:
“fc 7, xtal 2000, pll 1678” — this value differs.

I notice that every time I reboot, these two parameters are slightly different. Is this part of a crystal oscillator calibration process?

The pll should not have any impact. Could you please provide a project or bin file so we can reproduce the issue? Also, according to the configuration, SPI DMA uses CH5 and CH8, but why is there SPI-related configuration in CH7’s registers? Could this be a configuration error?

This afternoon, I’ll prepare a minimal project that can reproduce the issue.

Also, according to the configuration, SPI DMA is set to channels CH5 and CH8. However, why does CH7’s register also have SPI-related settings? Could this be a configuration error?

Here, I’ve modified the configuration later to assign SPI DMA to channels 7 and 8.

The binary file that reproduces the issue is attached;

sf32lb56_n16r12n1_bin.zip (3.2 MB)

Problem found when simplifying to minimal system:

We are using both SPI1 and SPI2 simultaneously. The issue does not occur if SPI1 configuration is removed.

Could you please help analyze the specific cause?

The minimal system is attached. You can replace sifli-sdk\\example\\hal\\spi\\src\\main.c to verify.

If the issue occurs, the following log prints:

10-20 16:39:39:266    [E/drv.spi] spi sem timeout!
10-20 16:39:39:268    [E/drv.spi] spi transfer errorB : 3, errcode=0
10-20 16:39:39:270    [D/DBG] rx::
10-20 16:39:39:271    0 0 0 0 0 0 0 0
10-20 16:39:39:272    0 0 0 0 0 0 0 0
10-20 16:39:39:272    [I/DBG] DMA ERROR 0

On your development board, connect via serial port and repeatedly press the reset button to reproduce the issue.

main.c (8.0 KB)

Hello, after using the bin file you provided to flash the device, we checked the DMA-related registers via tools and found that they do not match the description. According to the description, channel 7 and channel 8 should be enabled, but in the actual registers, only channel 1 and channel 2 have values. Moreover, both CPAR and CM0AR are 0, which appears as if the DMA is not working and SPI DMA hasn’t been enabled. Additionally, when we tried placing main.c into \example\hal\spi\src\main.c and compiling, errors occurred. Could you please provide the actual reproducible project?

image

After downloading the bin file and powering on, you need to press the power button once to enter SPI DMA mode.

When compiling the main file, you need to enable SPI2’s TX and RX DMA.

What exactly is the compilation error?

May I ask if this issue is still being tracked?

We can already reproduce the issue you mentioned, still looking for the cause. Please wait a bit longer.

I can’t compile the main function you provided here. You could try running rt_spi_configure twice inside spi2_init—that is, execute this line twice: “rst = rt_spi_configure(spi_dev_handle, &spi_dev_cfg);”—and see if the issue still occurs.

Can’t compile, is there an error? Do I need to configure DMA for SPI2?

Alright, I’ll get back to you after verification.